1. Field of the Invention
The present invention relates to semiconductor processing, and in particular, to methods for seamlessly filling gaps with high aspect ratio and a semiconductor device having seamless isolation structures therein.
2. Description of the Related Art
Typically, it is necessary in semiconductor processing to fill a high aspect ratio gap with insulating material. For example, like filling an inter-metal dielectric (IMD), inter-layer dielectric (ILD), pre-metal dielectric (PMD), and shallow trench isolation (STI) gap with un-doped oxide materials. As device dimensions shrink and thermal budgets are reduced, the seamless filling of high aspect ratio (AR) spaces (e.g., AR>4:1) has become increasingly difficult due to existing deposition process limitations. Currently, the method used for high aspect ratio (AR) gap-fill is deposition of an undoped oxide layer. Also, high density plasma chemical vapor deposition (HDP CVD) is used and a directional (bottom-up) CVD process.
Evolving semiconductor device designs and dramatically reduced feature sizes have resulted in several situations where HDP processes using current technologies may not be able to sufficiently fill high aspect ratio structures (e.g., AR>7:1). Therefore, an alternative to using CVD is atomic layer deposition (ALD). Adsorption of reactant gases are limited when using ALD and thin, conformal dielectric films with high aspect ratio features may be formed.
However, for sub 40 nm node technology, structures such as gaps or trenches with aspect ratios greater than 10:1 may be formed in a semiconductor device, and an undesired seam may be formed following gap-fill or filling of a trench using the ALD process. Thus, seamless gap filling is desired.